3D CT scan metrology for solder void formation analysis in ball grid array electronic chips

The miniaturization of silicon chips and the complexity of device functionality has driven the electronic packaging industry to find new methods to enhance the reliability of chips at a smaller size. Solutions such as Ball Grid Array (BGA) packages have contributed to the miniaturization of integrated circuits (ICs) and the reduction in their overall size. However, void formation in the solder joint is a weakness that can affect the robustness of the solder joint integrity, both mechanically and electrically. To detect these voids, metrology methods such as 3D Computed tomography (CT)-scan are used. 3D CT-scans can identify submicron-sized void defects in real-time during thermal tests, which can be utilized to help improve the quality control lines in the electronic chip manufacturing industries. In this paper, two types of BGA packages will be evaluated for solder joint properties. The prepared samples will be subject to high temperature stress conditions to assess the mechanism of void formation in solder joint. The prepared samples will be heated at 260 °C four times where the heating lasts 0, 5, 10, and 15 min, respectively. The prepared samples will be mounted on a PCB board and the results of the thermal stress tests will be analyzed using 3D X-ray CT scans. These 3D-CT scans used in tandem with a reconstruction and visualization software suite, will be utilized to observe changes such as void formation in the solder joint after each heating time. Unexpectedly, void size reduced between the first and second heat cycles on both samples but increased for the third and fourth heat cycles then.